What's New

• May 13, 2002 - See the course schedule for links to Lecture Notes and Lab Assignments.

Instructor

Professor John A. Nestor
Office: 412 Acopian Engineering Center
Office Hours: TBA
Phone: (610) 330-5411
E-mail: nestorj

Schedule

Lectures - MW 11-12:15, TBA
Laboratory - T 1:10-4:00, AEC 400

Course Description

This goal of this course is to build on your existing VLSI Design knowledge and gain experience designing VLSI Systems -  chips that implement complex functions.  This will require a more in-depth understanding of the Verilog HDL, an understanding of current design practice, especially verification of large HDL-based chip designs and design with timing constraints.  Additional coverage will include design issues for modern deep-submicron technologies (especially interconnect issues), the function,  capability, and limitations of VLSI CAD tools, and (possibly) the VHDL hadware description language.  A major part of the course will be a group design project in which we will design an interface chip for a simplified "Ethernet-like" network protocol that features collision detection and CRC error detection.  Last but not least, we will test the chips that were designed in ECE 425 and submit test reports for each chip to MOSIS..

ECE 425 - VLSI Circuit Design

Grading

Two In-Class Exams (Dates TBA)	50%
Lab Experiments & Homeworks	20%
Group Project	20%
Chip Testing / MOSIS Test Report	10%

Textbooks

1. Class Notes (distributed in class and online).
2. W. Wolf, Modern VLSI Design: Systems on Silicon, 2nd. ed.  Prentice-Hall, 1998.
3. ECE 426 Laboratory Manual (distributed in class and online)

References

1. J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd. ed., Prentice-Hall, 2003. (book homepage)
2. N. Weste & K. Eshraghian, Principles of CMOS VLSI Design , 2nd. ed., Addison-Wesley, 1993.
3. D. Smith and P. Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice-Hall, 2000
4. J. Bergeron, Writing Testbenches: Functional Verification of HDL Models
5. M. Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Prentice-Hall, 1999.
6. A. Rushton, VHDL for Logic Synthesis, 2nd. ed., John Wiley, 1998.